module top (
    input wire sw,
    output wire led1,
    output wire led2,
    output wire led3
    // output wire led4 // no hardware available
);

reg a;
reg b;
reg c;
reg d;

initial begin
    a = 1;
    b = 0;
    c = 1;
    d = 0;
end

always @ (posedge sw) begin
    a = b;
    b = a;
end

always @ (posedge sw) begin
    c <= d;
    d <= c;
end

assign led1 = a;
assign led2 = b;
assign led3 = c;
// assign led4 = d; // no hardware available

endmodule