module pipeline (
    input  wire       clk,
    input  wire [7:0] x,
    input  wire       in_valid,
    output wire [9:0] y,
    output wire       out_valid
);

reg [9:0] stage1;
reg [9:0] stage2;
reg [9:0] stage3;

reg valid1;
reg valid2;
reg valid3;

always @ (posedge clk) begin
    stage1 <= x + 1;
    stage2 <= stage1 * 2;
    stage3 <= stage2 + 3;
    
    valid1 <= in_valid;
    valid2 <= valid1;
    valid3 <= valid2;
end

assign y = stage3;
assign out_valid = valid3;

endmodule