`timescale 1ns / 1ps

module pipeline_tb;

reg clk;
reg [7:0] x;
reg valid_in;

wire [9:0] y;
wire valid_out;

pipeline dut (
    .clk(clk),
    .x(x),
    .in_valid(valid_in),
    .y(y),
    .out_valid(valid_out)
);

initial begin
    clk = 0;
end

always begin
    #10 clk = ~clk;
end

initial begin
    x = 0;
    valid_in = 0;

    @(negedge clk);
    x = 10;
    valid_in = 1;

    @(negedge clk);
    x = 99;
    valid_in = 0;

    @(negedge clk);
    x = 20;
    valid_in = 1;

    @(negedge clk);
    x = 88;
    valid_in = 0;

    @(negedge clk);
    x = 30;
    valid_in = 1;
end

initial begin
    #200;
    $finish;
end

endmodule