module pipeline (
    input  wire       clk,
    input  wire [7:0] x,
    input  wire       in_valid,
    output wire       in_ready,
    output wire [9:0] y,
    output wire       out_valid,
    input  wire       out_ready
);

reg  [9:0] stage1;
reg        valid1;
wire       ready1;

reg  [9:0] stage2;
reg        valid2;
wire       ready2;

reg  [9:0] stage3;
reg        valid3;
wire       ready3;

initial begin
    valid1 = 0;
    valid2 = 0;
    valid3 = 0;
end

assign ready3 = ~valid3 | out_ready;
assign ready2 = ~valid2 | ready3;
assign ready1 = ~valid1 | ready2;
assign in_ready = ready1;

always @ (posedge clk) begin
    if (ready1) begin
        stage1 <= x + 1;
        valid1 <= in_valid;
    end
    
    if (ready2) begin
        stage2 <= stage1 * 2;
        valid2 <= valid1;
    end
    
    if (ready3) begin
        stage3 <= stage2 + 3;
        valid3 <= valid2;
    end
end

assign y = stage3;
assign out_valid = valid3;

endmodule