`timescale 1ns / 1ps

module pipeline_tb;

reg        clk;

reg  [7:0] x;
reg        valid_in;
wire       ready_in;

wire [9:0] y;
wire       valid_out;
reg        ready_out;

pipeline dut (
    .clk(clk),
    
    .x(x),
    .in_valid(valid_in),
    .in_ready(ready_in),
    
    .y(y),
    .out_valid(valid_out),
    .out_ready(ready_out)
);

initial begin
    clk = 0;
end

always begin
    #10 clk = ~clk;
end

initial begin
    x = 0;
    valid_in = 0;

    @(posedge clk);
    while (!ready_in)
        @(posedge clk);
    
    @(negedge clk);
    x = 10;
    valid_in = 1;

    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 99;
    valid_in = 0;

    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 20;
    valid_in = 1;

    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 88;
    valid_in = 0;

    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 30;
    valid_in = 1;
    
    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 77;
    valid_in = 0;
    
    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 40;
    valid_in = 1;
    
    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 66;
    valid_in = 0;
    
    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 50;
    valid_in = 1;
    
    @(posedge clk);
    while (!ready_in)
        @(posedge clk);

    @(negedge clk);
    x = 60;
    valid_in = 1;
end

initial begin
    ready_out = 1;

    repeat (5) @(negedge clk);
    ready_out = 0;

    repeat (5) @(negedge clk);
    ready_out = 1;
    
    repeat (2) @(negedge clk);
    ready_out = 0;
    
    repeat (2) @(negedge clk);
    ready_out = 1;
end

initial begin
    #400;
    $finish;
end

endmodule