module top (
    input  wire clk,
    output wire led
);

reg [25:0] counter;
reg led_state;

initial begin
    counter = 0;
    led_state = 0;
end

always @(posedge clk) begin
    if (counter >= 26'd49_999_999) begin
        counter <= 0;
        led_state <= ~led_state;
    end
    else begin
        counter <= counter + 1;
    end
end

assign led = led_state;

endmodule