====== Assignment ======

There are 2 types of assignment: 

  * Blocking assignment ''=''
  * Non-blocking assignment ''<=''

They have different Verilog simulation semantics, which affects how a hardware description behaves and can cause simulation results to differ from the intended synchronous hardware behavior. In simulator, blocking assignment behaves like the programming language, the first line complete first (and blocking the next line to execute), then is the second line. While the the non-blocking assignment get ready all new values first, and then update all together.

For example, considering below program

<code verilog top.v [enable_line_numbers="true"]>
module top (
    input wire sw,
    output wire led1,
    output wire led2,
    output wire led3
    // output wire led4 // no hardware available
);

reg a;
reg b;
reg c;
reg d;

initial begin
    a = 1;
    b = 0;
    c = 1;
    d = 0;
end

always @ (posedge sw) begin
    a = b;
    b = a;
end

always @ (posedge sw) begin
    c <= d;
    d <= c;
end

assign led1 = a;
assign led2 = b;
assign led3 = c;
// assign led4 = d; // no hardware available

endmodule
</code>

The pair ''a''-''b'' is using blocking assignment. When at ''sw'' posegde, it will behave like

  - a=1, b=0. Initial condition. 
  - a=0, b=0. When sentence ''a = b;'' get executed. 
  - a=0, b=0. When sentence ''b = a;'' get executed. Since ''a'' already becomes 0, no changing will be observed. 

The pair ''c''-''d'' is using non-blocking assignment. 

  - c=1, d=0. Initial condition. 
  - c=1, d=0. c'=0, d'=1. Before ''sw'' posedge, new values are getting standby only. 
  - c=0, d=1. Once at ''sw'' posedge, both of them get updated at the same time.