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eee:fpga:led_blink [2026/08/15 09:36] – xiaobenmaoeee:fpga:led_blink [2026/08/15 13:17] (当前版本) – ↷ 链接因页面移动而自动修正 xiaobenmao
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 ===== Assignment ===== ===== Assignment =====
  
-Here we use ''<='' (non-blocking assignment) instead of ''='' (blocking assignment), and they have different Verilog simulation semantics, which affects how a hardware description behaves and can cause simulation results to differ from the intended synchronous hardware behavior. In simulator, blocking assignment behaves like the programming language, the first line complete first (and blocking the next line to execute), then is the second line. While the the non-blocking assignment get ready all new values first, and then update all together.  +Here we use ''<='' (non-blocking assignment) instead of ''='' (blocking assignment), and they have different Verilog simulation semantics, which affects how a hardware description behaves and can cause simulation results to differ from the intended synchronous hardware behavior. In simulator, blocking assignment behaves like the programming language, the first line complete first (and blocking the next line to execute), then is the second line. While the the non-blocking assignment get ready all new values first, and then update all together. Refer to page [[assignment]] for more details. 
- +
-Consider the initial condition ''a = 1'' and ''b = 2'', if blocking assignment is used,  +
- +
-<code verilog [enable_line_numbers="true"]> +
-a = b; +
-b = a; +
-</code> +
- +
-will get the result that ''a = 2'' and ''b = 2'', since the value of ''a'' has been updated before the phrase ''b = a;''.  +
- +
-The non-blocking assignment +
- +
-<code verilog [enable_line_numbers="true"]> +
-a <= b; +
-b <= a; +
-</code> +
- +
-can swap them nicely that ''a = 2'' and ''b = 1''. +
  
 For beginner, it is good to keep all sequential logic with non-blocking assignment ''<='', and combinational logic in blocking assignment ''=''.  For beginner, it is good to keep all sequential logic with non-blocking assignment ''<='', and combinational logic in blocking assignment ''=''. 
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 ===== Counting ===== ===== Counting =====
  
-The [[eee:fpga:board:ypcb-00338]] board have a crystal of 50 MHz (and also another 2 in 200 MHz). In order to toggle LED every 1 second, or 2 Hz, we need to count from 0 to 49,999,999, and then toggle ''led'' and reset counter. +The [[eee:fpga:board:ypcb-00338-1p1]] board have a crystal of 50 MHz (and also another 2 in 200 MHz). In order to toggle LED every 1 second, or 2 Hz, we need to count from 0 to 49,999,999, and then toggle ''led'' and reset counter. 
  
 <code verilog [enable_line_numbers="true"]> <code verilog [enable_line_numbers="true"]>
  • eee/fpga/led_blink.1786786614.txt.gz
  • 最后更改: 2026/08/15 09:36
  • 由 xiaobenmao