小笨猫知识灰库

jesd79-5 - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-23T14:33:29+00:00

JESD79-5 [ JESD79-5D v1.41]

jesd79-5d_v1.41_ddr5_sdram_202511.pdf - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-23T14:30:09+00:00

start

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T12:01:54+00:00

FPGA Fundamentals led_toggle led_blink calc_pipeline valid_ready fifo Connecting The World

calc_pipeline - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T11:59:46+00:00

Calc Pipeline Pipeline Consider the expression that $$ y = (x+1) \times 2 + 3 $$ where the input is $x$ and output is $y$. We would like to keep calculating what $x$ is feed in. It can be written that assign y = (x+1)*2+3; Assuming that each operation takes a time of $t$ to be stabilized, then the output $y$$3t$$3t$$0$$t$$t$$2t$$2t$$3t$$x$$x$$3t$$4t$$6t$$3t$

20260822-114337.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T11:43:37+00:00

20260822-090349.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T09:03:49+00:00

20260822-084636.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T08:46:36+00:00

20260822-084247.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T08:42:47+00:00

20260822-084147.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T08:41:47+00:00

20260822-083725.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-22T08:37:25+00:00

ypcb-00338 - ↷ 页面名由eee:fpga:board:ypcb-00338改为eee:fpga:board:ypcb-00338-1p1

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T13:17:17+00:00

ypcb-00338-1p1 - ↷ 页面名由eee:fpga:board:ypcb-00338改为eee:fpga:board:ypcb-00338-1p1

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T13:17:17+00:00

YPCB-00338-1P1 FPGA: XC7K480TFFG1156-2 Interface User Interface 板上共有 6 粒 LED，其中 LED1、LED2 位于板卡正面左上角，LED3 至 LED6 位于后方挡板，从上至下分别为 LED6、LED3、LED5、LED4。 LED color pin standard

dspic30f6010 - 已恢复为旧版 (2026/08/15 13:02)

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T13:02:57+00:00

dsPIC30F6010

dspic30f6010 - ↷ 页面eee:mcu:dspic30f6010被移动至eee:mcu:chip:dspic30f6010

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T13:02:15+00:00

led_blink

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T12:55:28+00:00

LED Blink Create an empty project like led_toggle did. Clock Sequential RTL usually describes behavior in terms of clock edges rather than absolute time. always @(posedge clk) reacts to each rising edge regardless of whether the clock is 50 MHz or 100 MHz. However, the physical circuit does care about the clock period, because the combinational logic between registers must settle before the next sampling edge.$$ 2^{25} = 33,554,432 < 50,000,000 \\ 2^{26} = 67,108,864 > 50,000,000 $$

assignment - 已恢复为旧版 (2026/08/15 12:53)

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T12:54:54+00:00

Assignment There are 2 types of assignment: * Blocking assignment = * Non-blocking assignment <= They have different Verilog simulation semantics, which affects how a hardware description behaves and can cause simulation results to differ from the intended synchronous hardware behavior. In simulator, blocking assignment behaves like the programming language, the first line complete first (and blocking the next line to execute), then is the second line. While the the non-blocking assignmen…

ssignment - ↷ 页面名由eee:fpga:ssignment改为eee:fpga:assignment

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T12:53:57+00:00

20260815-091250.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T09:12:50+00:00

20260815-084711.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-15T08:47:11+00:00

20260812-151856.png - 创建

xiaobenmao (xiaobenmao@undisclosed.example.com) — 2026-08-12T15:18:56+00:00