Assignment

There are 2 types of assignment:

They have different Verilog simulation semantics, which affects how a hardware description behaves and can cause simulation results to differ from the intended synchronous hardware behavior. In simulator, blocking assignment behaves like the programming language, the first line complete first (and blocking the next line to execute), then is the second line. While the the non-blocking assignment get ready all new values first, and then update all together.

For example, considering below program

top.v
  1. module top (
  2.     input wire sw,
  3.     output wire led1,
  4.     output wire led2,
  5.     output wire led3
  6.     // output wire led4 // no hardware available
  7. );
  8.  
  9. reg a;
  10. reg b;
  11. reg c;
  12. reg d;
  13.  
  14. initial begin
  15.     a = 1;
  16.     b = 0;
  17.     c = 1;
  18.     d = 0;
  19. end
  20.  
  21. always @ (posedge sw) begin
  22.     a = b;
  23.     b = a;
  24. end
  25.  
  26. always @ (posedge sw) begin
  27.     c <= d;
  28.     d <= c;
  29. end
  30.  
  31. assign led1 = a;
  32. assign led2 = b;
  33. assign led3 = c;
  34. // assign led4 = d; // no hardware available
  35.  
  36. endmodule

The pair a-b is using blocking assignment. When at sw posegde, it will behave like

  1. a=1, b=0. Initial condition.
  2. a=0, b=0. When sentence a = b; get executed.
  3. a=0, b=0. When sentence b = a; get executed. Since a already becomes 0, no changing will be observed.

The pair c-d is using non-blocking assignment.

  1. c=1, d=0. Initial condition.
  2. c=1, d=0. c'=0, d'=1. Before sw posedge, new values are getting standby only.
  3. c=0, d=1. Once at sw posedge, both of them get updated at the same time.