LED Toggle

Create a new RTL project named 00338_led_toggle, select xc7k480tffg1156-2 part (or the actual device using)

Add new design source top.v to the project, with the content below.

top.v

module top (
    input  wire sw,
    output wire led
);
 
assign led = ~sw;
 
endmodule

There is a module (not the filename) named top. A module is a block of circuit that is able to perform specific function. Here, it defines an input signal sw and an output signal led. Both of the signal have the type of wire, which represents a net (connection) between hardware elements. It does not store a value by itself; its value is determined by whatever drives it. The assign describes continuous combinational logic. assign led = ~sw; means led continuously follows the inverse of sw. ~ operator is bitwise invert of a signal, like some programming languages. That is, if sw is 0(low), led will be 1(high), and if sw is 1, led will be 0. module need to be completed by endmodule phrase.

The module top only describes how the circuit behaves, but we don't know where the signals connected to. Constraint file is used to specify the connection from our signal to physical IO pins. To create a constraint file, similarly we can create a top.xdc file to the project.

top.xdc

set_property PACKAGE_PIN R28 [get_ports sw]
set_property IOSTANDARD LVCMOS18 [get_ports sw]

set_property PACKAGE_PIN P30 [get_ports led]
set_property IOSTANDARD LVCMOS18 [get_ports led]

Now we telling that the signal sw is physically connected to pin R28 using IO standard LVCMOS18, and also led is P30 with LVCMOS18. The choice of LVCMOS18 is not a random option, it must follow the design of peripherals that the pin connected to, and must be compatible to the VCCO supply of the IO bank.

For your information, the LVCMOS18 standard specify the voltage as below:

Now click “Generate Bitstream”, which will perform tasks like a compiler, to perform a series operation including synthesis and implementation, to convert our project to a FPGA-readable content. Once completed, it can be downloaded to the FPGA device via the “Hardware Manager”.

The device is expected to behave like what above codes describe: when pressing SW2, red LED light up, and the LED blow once release SW2. Be careful not to touch SW1 which will clear the currently downloaded FPGA chip configuration. If SW1 get pressed accidentally, re-download the bitstream.